In power applications involving an integrated circuit control element, an inductive load is typically driven by a power field effect transistor (FET). When the transistor is turned off, the inductive load will have a fly-back voltage associated therewith due to the inductive storage of energy therein. This fly-back will cause the voltage on the drain of an N-channel FET utilized for the driving element to rise to a relatively high level. These FETs can be damaged by flyback-induced voltage excursions that rise to a level above the junction breakdown of the FET.
In order to protect the FET, a clamp circuit is typically connected between the drain and gate of the FET. When the voltage on the drain of the FET rises to a sufficiently high level, current will conduct through the clamp, pulling the gate of the FET high and turning on the FET, this effectively preventing the fly-back voltage from pulling the drain above the clamp voltage. These clamp circuits utilized in the prior art circuits consisted of a series of zener diodes, each having a breakdown voltage that, when added together, comprise the overall threshold voltage for the clamp.
One disadvantage to prior art clamp circuits is the current level that must be accommodated by the clamp. Whenever the fly-back voltage pulls the drain of the FET high, current will flow from the drain to the gate, some passing through the driving circuit that drives the FET. This is a finite amount of current, which can be sufficiently high to require relatively robust components in the clamp. However, the design of a clamp circuit that will accommodate the necessary levels current require relatively large devices. This can become a disadvantage in that the clamp circuits are typically incorporated into the integrated circuit output that drives the FET.